1. Field of the Invention
The present invention relates generally to electronic packaging and, more particularly, to a method of wire bonding, a semiconductor chip, and a semiconductor package.
2. Description of the Related Art
In general, an electronic package is defined as the housing and interconnection of integrated circuits, also referred to as ‘semiconductor device’, ‘chip’ or ‘die’, to form an electronic system. The package should provide a structure to physically support the chip and to protect the chip from the environment, means for removing heat generated by the chips or system, and/or electrical connections to provide signal and power access to and from the chip.
Wire bonding technology is a conventional technique used to make electrical connections within the package. Wire bonding may employ gold, aluminum, or copper wires. A wire is bonded at one end to the chip and at the other end to a next-level substrate such as a lead frame, a printed circuit board, a ceramic substrate, or a flexible circuit board.
A conventional technique of wire bonding is to form a ball bond on the chip and a stitch bond on the substrate. More particularly, a ball is formed on a tail of the wire, which extends from the end of a capillary of a wire bonder, and is bonded to a bond pad of the chip under pressure by the capillary while heat and/or ultrasonic vibration are applied. After the ball bond is formed, a loop is formed in the wire by subsequent action of the capillary. The capillary deforms the wire against a bond position of the substrate, producing a wedge-shaped stitch bond. The cycle is then completed and the next ball bond can be formed.
This wire bonding technique requires sufficient height of the wire over the top of the chip so as to produce and maintain a stable loop in the wire. Though it may depend on a diameter of the wire, the height of the wire above the chip may be at least one hundred micron (100 μm). This extra height may impede the ability to make thinner packages.
In order to solve the above problem, a conventional bump reverse bonding technique has been developed. In this technique, a ball bond is formed on the substrate, whereas a stitch bond is formed on the chip. The stitch bond on the chip is made possible placing a ball bump on the bond pad of the chip. The stitch bond on the chip provides a connection without a loop over the bond pad. Related techniques are disclosed in U.S. Pat. Nos. 5,328,079 and 5,735,030, and Korean Patent No. 0350084.
The bump reverse bonding, however, encounters an increase in process time due to unnecessary motion of the capillary. FIG. 7 shows the motion of the capillary in a conventional bump reverse bonding. Referring to FIG. 7, initially, the capillary (not shown) is located above the bond pad 52 of the chip 50 to form a ball bump 82. After the ball bump 82 is formed on the bond pad 52, the capillary moves toward the bond position 62 of the substrate. Then the capillary performs a ball bonding on the bond position 62 and returns to the chip 50 for a stitch bond on the bond pad 52.
As described above, the conventional bump reverse bonding requires the capillary to travel from the bond pad 52 to the bond position 62 and back again to connect one bond pad 52 of the chip 50 and one bond position 62 of the substrate. As shown in FIG. 7, a movement of the capillary from the bond pad 52 to the bond position 62, depicted as a dotted line is only to transfer the wire, rather than to connect the wire. Movement of the capillary depicted as a solid line represents a motion of the capillary to connect the wire, rather than just transfer the wire.